SI4022-A0-FT【PDF 9/20 页】IC TX FSK UNI 868/915MHZ 16TSSOP

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Si4022

CONTROL INTERFACE

Commands to the transmitters are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on

pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. The number of bits

sent is an integer multiple of 8 (except for the Transmitter FIFO Write Command). All commands consist of a command code,

followed by a varying number of parameter or data bits. All data are sent MSB first (e.g. bit 15 for a 16-bit command). Bits having no

influence (dont care) are indicated with X. The Power On Reset (POR) circuit sets default values in all control and command

registers.

Timing Specification

Timing Diagram

SCK

SDI

SDO

nSEL

BIT15

BIT14

BIT13

BIT8

BIT7

BIT1

BIT0

SHI

BIT15

BIT14

BIT1

BIT0

BIT8

BIT7

BIT13

Symbol

Parameter

Minimum value [ns]

Clock high time

Clock low time

Select setup time (nSEL falling edge to SCK rising edge)

Select hold time (SCK falling edge to nSEL rising edge)

SHI

Select high time

Data setup time (SDI transition to SCK rising edge)

Data hold time (SCK rising edge to SDI transition)

Data delay time

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